Downloads About Manual Tutorials Publications Lectures

  • "CppSim/VppSim is a great tool for high-speed link applications to achieve both fine timing accuracy and speed when capturing interactions between adaptive equalization algorithms and clock-and-data-recovery loops. Links typically require simulation of long bit sequences in order to capture intersymbol interference effects and examine loop dynamics which are typically orders of magnitude slower than the symbol rate. This puts a real challenge on typical behavioral simulators, but CppSim/VppSim performs very well in this space. In the Integrated Systems Group at MIT, we have been using the tool to design adaptive oversampled equalization filters that replace the CDR/symbol-space equalizer combination at the receiver. Using VppSim has helped us tremendously in speeding up the design process from algorithm to circuit implementation."
    Prof. Vladimir Stojanovic, MIT
  • "At Fairchild, we use CppSim to develop new circuit architectures for MEMs gyroscopes and other MEMs-based sensor platforms (these are high-Q, mixed-signal systems with digital content represented as Verilog code). Verilog-A is also an option, but writing Verilog-A code to optimize for speed, accurate noise modeling and error-free simulations is challenging. CppSim, on the other hand, provides fast, accurate, and headache-free transient noise simulation results with relative ease. Given its full compatibility with the Cadence environment, co-sim ability with Verilog, use of analogLib-style primitives, and its fast learning curve, CppSim has become our system simulation tool of choice to evaluate innovative mixed-signal architectures going well beyond PLL circuits."
    Fred S. Lee, Principle IC Designer, Fairchild Semiconductor
  • "I've been using CppSim myself for many years now. I used all versions of this fantastic tool as well as its Verilog-AMS compatible version, VppSim. Its phenomenal speed advantage and ease of use make it an indispensable tool for frequency synthesizers and CDR designers. We were able to build multiple Fractional-N PLL synthesizers and optimize their performance in short times using CppSim. We found it to be the shortest path to design all-digital PLLs as well."
    Emad Hegazi, General Manager RF/AMS SySDSoft Inc
  • "Cambridge Analog Technologies (CAT) has found CppSim / VppSim to be very useful in the design of high-performance mixed-signal IP, such as low-jitter digital PLL and low-power high-resolution ADC. The unique combination of simulation speed, timing accuracy, flexibility, and digital verification capability that CppSim/VppSim offers as a supplement to the traditional EDA design flow is a great asset for our designers."
    Matthew Straayer, Cambridge Analog Technologies (CAT)
  • "Vppsim within the Cadence environment has been the tool of choice at PhaseLink for the evaluation of advanced PLL synthesizer architectures. CppSim simulation of C++ modules runs very fast while still including key relevant timing details. The rich C++ class set of CppSim allows easy implementation of a multiplicity of alternative architectures. Schematic descriptions work naturally and intuitively for architectural enhancements. The signal outputs sampled at constant rate are easily probed for powerful post-processing within Matlab. Further, the embedding of Vppsim modules within Cadence AMS allows for flexible functional debugging of the architecture using more detailed Verilog implementations. Co-simulation with Spectre validates the behavioral models against device-level implementations."
    Pierre Guebels, PhaseLink Corporation
  • "CppSim has become our 'go-to' tool for investigating new PLL architectures. The students love it. As an example it was critical to our success in digital-dominant frac-N PLLs."
    Professor Michael Flynn, University of Michigan
  • "When I finally got around to simulating digital PLLs in CppSim, I was stunned at how easy it was to reproduce all of the key features of their behavior and to find answers to some of the questions/problems that we knew we had but could not resolve for a long time."
    Alexander Rylyakov,IBM T.J. Watson Research Center
  • "Designing precision timing circuits that exhibit grossly non-linear behavior requires performing accurate simulations in the time domain. Such simulations take prohibitively long, even in commercial behavioral simulators, which have often limited our ability to evaluate new PLL, CDR, and ADC architectures in the past. CppSim and its Cadence compatibility have filled this void and have been instrumental in the design of many of the digital PLLs/CDRs and time-based ADCs designed in my research group. Because of its high accuracy, using CppSim has also enabled us to evaluate the noise performance of our PLLs/CDRs/ADCs rapidly. The students liked the ease of use, specifically in simulating oscillators with phase noise."
    Pavan Kumar Hanumolu, Assistant Professor, Oregon State University
  • "Analog Bits low power, programmable SERDES supports numerous industry standard protocols and concurrent modeling time of analog and digital circuits within SERDES is important. Using CppSim we have reduced SERDES modeling time by a factor of four verses a traditional custom C-code model and this has helped us to deliver high quality SERDES in a timely manner to our customers."
    Mark Marlett, Director of Engineering, Analog Bits Inc.

CppSim automatically generates, compiles, and runs C++ code corresponding to the schematic design that you create.

Graphical Interface:

Systems are specified and simulated within a schematic editor, Sue2, and results are viewed using a waveform viewer (CppSimView or GTKWave).

Analog modules:

A simple text template for each module is filled in by the user which can make use of a rich set of C++ classes to represent common functions such as filtering, noise, etc.

Digital modules:

CppSim utilizes Verilator to automatically create C++ code corresonding to your Verilog modules, and seamlessly integrates this code into your system simulation.

Linear networks and switches:

CppSim automatically creates a C++ state-space representation of linear networks with switches in your schematic design, and seamlessly includes this code in the simulation.

Verilog Testbenches:

VppSim combines Verilog with CppSim to seamlessly include C++ modules and linear networks with switches with Verilog as specified within a schematic driven framework.

Spice Simulation:

NGspice is included as a standalone tool for transistor level simulations and utilizes the schematic editor and waveform viewer of the CppSim framework.

Postprocessing with Python, Matlab®, and Octave

CppSim simulations are easily read into Python, Matlab®, and Octave to allow seamless postprocessing of your results.

Try it:

Click the Download button to install, and start with the CppSim Primer in the Manuals section to learn how to use the tool.