Publications

CppSim has served as a valuable tool in the development of new architectures for custom integrated circuits. The publications listed here are the outcome of research done at MIT in this area by Michael Perrott and his former students, and may be a useful reference for those interested in the CppSim package. In particular, some of the tutorials are based on work described in the publications listed here.

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The joint paper with Kärtner below was published in Optics Letters and is made available as an electronic reprint with the permission of OSA. One print or electronic copy may be made for personal use only. Systematic or multiple reproduction, distribution to multiple locations via electronic or other means, duplication of any material in this paper for a fee or for commercial purposes, or modification of the content of the paper are prohibited. Copyright OSA (OSA Journals weblink: http://www.osa.org/pubs/osajournals/).

Communication Circuits

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  • Min Park, M.H. Perrott, R.B. Staszewski "An Amplitude Resolution Improvement of an RF-DAC Employing Pulsewidth Modulation," IEEE Trans. on Circuits and Systems I - Regular Papers, Vol. 58, Issue 11, 2011, pp. 2590-2603.
  • Min Park, M.H. Perrott, R.B. Staszewski, "A Time-Domain Resolution Improvement of an RF-DAC," IEEE Trans. on Circuits and Systems II - Express Briefs, Vol. 57, July 2010, pp. 517-521.
  • Min Park, M.H. Perrott, "A Multiphase PWM RF Modulator Using a VCO-Based Opamp in 45nm CMOS," Radio Frequency Integrated Circuits (RFIC) Symposium 2010, May 2010.
  • Kim, M.J. Park, M.H. Perrott, F.X. Kaertner, "Photonic subsampling analog-to-digital conversion of microwave signals at 40-GHz with higher than 7-ENOB resolution," Optics Express, Vol. 16, No. 21, 13 Oct 2008
  • M. Park, J-W Kim, F. Kaetner, M.H. Perrott, "An Optical-Electrical Sub-Sampling Receiver Employing Continuous-Time ΣΔ Modulation," ESSCIRC 2006 Dig. Tech. Papers, Sep. 2006, pp. 182-185
  • E.A. Crain, M.H. Perrott, "A 3.125 Gb/s Limit Amplifier in CMOS with 42 dB Gain and 1us Offset Compensation," IEEE J. Solid-State Circuits, vol. 41, pp. 443-451, Feb. 2006.
  • E. Crain, M. Perrott, "A 3.125Gb/s Limit Amplifier with 42dB Gain and 1μs Offset Compensation in 0.18um CMOS," in ISSCC 2005 Dig. Tech. Papers, Feb. 2005, pp. 232-233, 595.

Analog-to-Digital Conversion

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  • Matthew Park, M.H. Perrott, "A 78 dB SNDR 87 mW 20 MHz Bandwidth Continuous-Time Delta-Sigma ADC With VCO-Based Integrator and Quantizer Implemented in 0.13 um CMOS," IEEE J. Solid-State Circuits, vol. 44, Dec 2009, pp. 3344-3358
  • Min Park, M.H. Perrott, "A Single-Slope 80 MS/s ADC using Two-Step Time-to-Digital Conversion," ISCAS 2009, May 2009, pp. 1125-1128.
     
  • Min Park, M.H. Perrott, "A VCO-based Analog-to-Digital Converter with Second-Order Sigma-Delta Noise Shaping", ISCAS 2009, May 2009, pp. 3130-3133
  • M. Park, M.H. Perrott, "A 0.13um CMOS 78dB SNDR 87mW 20MHz BW CT Delta-Sigma ADC with VCO-Based Integrator and Quantizer," ISSCC 2009 Dig. Tech. Papers, Feb. 2009, pp. 170-171
  • M.Z. Straayer, M.H. Perrott, "A 12-bit 10-MHz Bandwidth, Continuous-Time Sigma-Delta ADC With a 5-Bit, 950-MS/S VCO-based Quantizer," IEEE J. Solid-State Circuits, vol. 43, April 2008, pp. 805-814
  • M.Z. Straayer, M.H. Perrott, "A 10-bit 20MHz 38mW 950MHz CT ΣΔ ADC with a 5-bit noise-shaping VCO-based Quantizer and DEM circuit in 0.13u CMOS," IEEE VLSI Circuits Symp., Jun. 2007, pp. 246-247.

Highly Digital Phase Locked Loops
and Time-to-Digital Conversion

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  • B.M. Helal, C.-M. Hsu, K. Johnson, M.H. Perrott, "A Low Jitter Programmable Clock Multiplier Based on a Pulse Injection-Locked Oscillator With a Highly-Digital Tuning Loop," IEEE J. Solid-State Circuits, vol. 44, May 2009, pp. 1391-1400
  • M.Z. Straayer, M.H. Perrott, "A Multi-Path Gated Ring Oscillator TDC With First-Order Noise Shaping ," IEEE J. Solid-State Circuits, vol. 44, April 2009, pp. 1089-1098
  • C.-M. Hsu, M.Z. Straayer, M.H. Perrott, "A Low-Noise Wide-BW 3.6-GHz Digital Delta-Sigma Fractional-N Frequency Synthesizer With a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation," IEEE J. Solid-State Circuits, vol. 43, Dec. 2008, pp. 2776-2786
  • M.Z. Straayer, M.H. Perrott, "An efficient high-resolution 11-bit noise-shaping multipath gated ring oscillator TDC," IEEE VLSI Circuits Symp., Jun. 2008, pp. 82-83.
  • B.M. Helal, C.-M. Hsu, K. Johnson, M.H. Perrott, "A Low Noise Programmable Clock Multiplier based on a Pulse Injection-Locked Oscillator with a Highly-Digital Tuning Loop," Radio Frequency Integrated Circuits (RFIC) Symposium 2008, June 2008.
  • B.M. Helal, M.Z. Straayer, M.H. Perrott, "A Highly Digital Clock Multiplier That Leverages a Self-Scrambling Time-to-Digital Converter to Achieve Subpicosecond Jitter Performance," IEEE J. Solid-State Circuits, vol. 43, April 2008, pp. 855-863.
  • C.-M. Hsu, M.Z. Straayer, M.H. Perrott, "A Low-Noise, Wide-BW 3.6GHz Digital Delta-Sigma Fractional-N Frequency Synthesizer with a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation," ISSCC 2008 Dig. Tech. Papers, Feb. 2008, pp. 340,617
  • B.M. Helal, M.Z. Straayer, G-Y Wei, M.H. Perrott, "A Low Jitter 1.6 GHz Multiplying DLL Utilizing a Scrambling Time-to-Digital Converter and Digital Correlation," IEEE VLSI Circuits Symp., Jun. 2007, pp. 166-167.
  • M.H. Perrott, Y. Huang, R.T. Baird, B.W. Garlepp, D. Pastorello, E.T. King, Q. Yu, D.B. Kasha, P. Steiner, L. Zhang, J. Hein, B. Del Signore, "A 2.5 Gb/s Multi-Rate 0.25μm CMOS Clock and Data Recovery Circuit Utilizing a Hybrid Analog/Digital Loop Filter and All-Digital Referenceless Frequency Acquisition," IEEE J. Solid-State Circuits, vol. 41, Dec. 2006, pp. 2930-2944
  • M.H. Perrott, Y. Huang, R.T. Baird, B.W. Garlepp, L. Zhang, J.P. Hein, "A 2.5 Gb/s Multi-Rate 0.25μm CMOS CDR Utilizing a Hybrid Analog/Digital Loop Filter," ISSCC 2006 Dig. Tech. Papers, Feb. 2006, pp.1276,1285

Analog Phase Locked Loops

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  • C-M Hsu, C.Y. Lau, M.H. Perrott, "A Delay-Locked Loop using a Synthesizer-Based Phase Shifter for 3.2 Gb/s Chip-to-Chip Communication," ESSCIRC 2006 Dig. Tech. Papers, Sep. 2006, pp. 460-463
  • S.E. Meninger, M.H. Perrott, "A 1-MHZ Bandwidth 3.6-GHz 0.18-um CMOS Fractional-N Synthesizer Utilizing a Hybrid PFD/DAC Structure for Reduced Broadband Phase Noise," IEEE J. Solid-State Circuits, vol. 41, Apr. 2006, pp. 966-980.
  • S.E. Meninger, M.H. Perrott, "A Dual Band 1.8GHz/900MHz, 750kb/s GMSK Transmitter Utilizing a Hybrid PFD/DAC Structure for Reduced Broadband Phase Noise," IEEE VLSI Circuits Symp., Jun. 2005.
  • S.E. Meninger, M.H. Perrott, "Bandwidth Extension of Low Noise Fractional-N Synthesizers," Radio Frequency Integrated Circuits (RFIC) Symposium 2005, Jun. 2005.
  • J. Kim, F. X. Kärtner, M. H. Perrott, "Femtosecond synchronization of radio frequency signals with optical pulse trains," Optics Letters, vol. 29, Issue 17, Sep. 2004, pp. 2076-2078.
  • S.E. Meninger, M.H. Perrott, "A fractional-N frequency synthesizer architecture utilizing a mismatch compensated PFD/DAC structure for reduced quantization-induced phase noise," IEEE Trans. Circuits Syst. II, vol. 50, Nov. 2003, pp. 839-849
  • M.H. Perrott, T.L. Tewksbury, C.G. Sodini, "A 27-mW CMOS fractional-N synthesizer using digital compensation for 2.5-Mb/s GFSK modulation," IEEE J. Solid-State Circuits, vol. 32, Dec. 1997, pp. 2048-2060.
  • M.H. Perrott, T.L. Tewksbury, C.G. Sodini, "A 27mW CMOS fractional-N synthesizer/modulator IC," in ISSCC 1997 Dig. Tech. Papers, Feb. 1997, pp. 366-367, 487.

MEMS-based Clocking Techniques

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  • M.H. Perrott, J.C. Salvia, F.S. Lee, A. Partridge, S. Mukherjee, C. Arft, J.-T. Kim, N. Arumugam, P. Gupta, S. Tabatabaei, S. Pamarti, H.-C. Lee, F. Assaderagi, "A Temperature-to-Digital Converter for a MEMS-Based Programmable Oscillator With < +/- 0.5-ppm Frequency Stability and < 1-ps Integrated Jitter," IEEE J. Solid-State Circuits, vol. 48, Jan 2013
  • M.H. Perrott, J.C. Salvia, F.S. Lee, A. Partridge, S. Mukherjee, C. Arft, J.-T. Kim, N. Arumugam, P. Gupta, S. Tabatabaei, S. Pamarti, H.-C. Lee, F. Assaderagi, "A Temperature-to-Digital Converter for a MEMS-Based Programmable Oscillator with Better Than +/- 0.5ppm Frequency Stability," ISSCC 2012 Dig. Tech. Papers, Feb. 2012, pp. 206-207
  • F.S. Lee, J. Salvia, C. Lee, S. Mukherjee, R. Melamud, N. Arumugam, S. Pamarti, C. Arft, P. Gupta, S. Tabatabaei, B. Garlepp, H.-C. Lee, A. Partridge, M.H. Perrott, F. Assaderagi, "A programmable MEMS-Based clock generator with sub-ps jitter performance," IEEE VLSI Circuits Symp., Jun. 2011, pp. 158-159
  • M.H. Perrott, S. Pamarti, E.G. Hoffman, F.S. Lee, S. Mukherjee, C. Lee, V. Tsinker, S.Perumal, B.T. Soto, N. Arumugam, B.W. Garlepp, "A Low Area, Switched-Resistor Based Fractional-N Synthesizer Applied to a MEMS-Based Programmable Oscillator," IEEE J. Solid-State Circuits, vol. 45, Dec 2010, pp. 2566-2581
  • M.H. Perrott, S. Pamarti, E. Hoffman, F.S. Lee, S. Mukherjee, C. Lee, V. Tsinker, S.Perumal, B. Soto, N. Arumugam, B.W. Garlepp, "A Low-Area Switched-Resistor Loop-Filter Technique for Fractional-N Synthesizers Applied to a MEMS-Based Programmable Oscillator," ISSCC 2010 Dig. Tech. Papers, Feb. 2010, pp. 244-245

Analysis and Simulation Techniques

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  • E.A. Crain, M.H. Perrott, "A Numerical Design Approach for High-Speed, Differential, Resistor-Loaded, CMOS Amplifiers," IEEE International Symposium on Circuits and Systems (ISCAS '04), May 2004.
  • C.Y. Lau, M.H. Perrott, "Phase Locked Loop Design at the Transfer Function Level Based on a Direct Closed Loop Realization Algorithm", Design Automation Conference (DAC), Jun. 2003, pp. 526-531
  • M.H. Perrott, M.D. Trott, C.G. Sodini, "A modeling approach for Σ-Δ fractional-N frequency synthesizers allowing straightforward noise analysis," IEEE J. Solid-State Circuits, vol. 37, pp. 1028-1038, Aug. 2002.
  • M.H. Perrott, "Behavioral simulation of fractional-N frequency synthesizers and other PLL circuits," IEEE Design & Test of Computers, vol. 19, pp. 74-83, Jul. 2002.
  • M.H. Perrott, "Fast and Accurate Behavioral Simulation of Fractional-N Synthesizers and other PLL/DLL Circuits", Design Automation Conference (DAC), Jun. 2002, pp 498-503.

Miscellaneous

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  • M. Alhawari, M.H. Perrott, "A Clockless, Multi-Stable, CMOS Analog Circuit," ISCAS 2014, June 2014, pp. 1764-1767.
     
  • W. Saadeh, T. Tekeste, M.H. Perrott, "A >89% Efficient LED Driver with 0.5V Supply Voltage for Applications Requiring Low Average Current," A-SSCC 2013, Nov. 2013, pp. 273-276
  • M. Alhawari, N. Albelooshi, M.H. Perrott, "A 0.5V <4uW CMOS Light-to-Digital Converter Based on a Non-Uniform Quantizer for a Photoplethysmographic Heart-Rate Sensor," IEEE J. Solid-State Circuits, vol. 49, January 2014, pp. 271-288
  • M. Alhawari, N. Albelooshi, M.H. Perrott, "A 0.5V <4uW CMOS Photoplethysmographic Heart-Rate Sensor IC Based on a Non-Uniform Quantizer," ISSCC 2013 Dig. Tech. Papers, Feb. 2013, pp. 384-385
  • M.H. Perrott, R.J. Cohen, "An Efficient Approach to ARMA Modeling of Biological Systems with Multiple Inputs and Delays," IEEE Transactions on Biomedical Engineering, vol. 43, Jan. 1996, pp. 1-14

Theses

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  • M.J. Park, "A 4th Order Continuous-Time ΔΣ ADC with VCO-Based Integrator and Quantizer," PhD Thesis, MIT, February 2009.
     
  • C.-M. Hsu, "Techniques for High-Performance Digital Frequency Synthesis and Phase Control," PhD Thesis, MIT, September 2008.
     
  • M.Z. Straayer, "Noise Shaping Techniques for Analog and Time to Digital Converters Using Voltage Controlled Oscilllators," PhD Thesis, MIT, June 2008.
  • B.M. Helal, "Techniques for Low Jitter Clock Multiplication," PhD Thesis, MIT, June 2008.
     
  • S.E. Meninger, "Low Phase Noise, High Bandwidth Frequency Synthesis Techniques", PhD Thesis, MIT, May 2005.
     
  • S. Kuo, "Linearization of a Pulse Width Modulated Power Amplifier," June 2004.
     
  • E.A. Crain, "Fast Offset Compensation for a 10 Gbps Limit Amplifier," May 2004.
     
  • M.H. Perrott, "Techniques for High Data Rate Modulation and Low Power Operation of Fractional-N Frequency Synthesizers," Sept. 1997.